Although there is, for example, a silicon substrate which is generally used as a semiconductor substrate used in an integrated circuit, a semiconductor device with high speed and low power consumption is further required with improvement in speed and high integration of a system or development of a mobile terminal in recent years.
Under such a background, an SOI wafer having a SOI (Silicon On Insulator) structure in which a silicon active layer (SOI layer) is formed on an insulated layer can meet operation of devices with higher speed and low power consumption, and if the SOI wafer is used, device fabrication can be made without a significant change in established equipment, processes, or the like of device processes for a bulk wafer which does not have the SOI structure, so that the SOI wafer has been attracting attention as a wafer that can realize the operation of the devices with higher speed and low power consumption.
A general structure of such an SOI wafer is shown in FIG. 4. In an SOI wafer 10, a SOI layer 15 is formed on a supporting substrate 13 composed of silicon single crystal or the like so as to dispose a buried insulated layer 14 therebetween. Further, for convenience of the device fabrication or for the purpose of adding gettering capability or the like, a buried diffusion layer 12 in which impurities are diffused in high concentration is formed in an interface region in the SOI layer 15 with the insulated layer 14 in some cases as shown in FIG. 4. As forming in this way, the SOI layer 15 has the buried diffusion layer 12 and a low concentration layer 11 whose impurity concentration is lower than that in the buried diffusion layer.
The SOI wafer has been attracting a lot of attention as described above and accurate evaluation of characteristics of the SOI wafer has been required, so that various researches on the evaluation method have been currently conducted.
For example, evaluation of the characteristics on a surface of the SOI layer can be performed by contacting an electrode and a probe on front and back surfaces of the SOI wafer for measurement as disclosed in, for example, Japanese Unexamined Patent Publication (Kokai) No. 2000-277716, without using a four-point probe method. On the other hand, the buried diffusion layer 12 is buried in the SOI wafer, so that evaluation of characteristics of the layer has been difficult.
Conventionally, evaluation of sheet resistance of the buried diffusion layer of the SOI wafer has been performed by simultaneously fabricating a monitor wafer separately when manufacturing an SOI wafer to be a product as shown in, for example, FIG. 6.
Hereinafter, an example of a method for fabricating this monitor wafer to evaluate the sheet resistance of the buried diffusion layer will be described briefly.
First, while preparing a base wafer and a bond wafer for manufacturing the SOI wafer to be the product by a bonding method, a wafer to be the monitor wafer is prepared (a). Next, an oxide film is formed on the front surface of the base wafer (Box oxidization) (b). Next, screen oxidization of the surface (c) and impurity ion implantation (d) are simultaneously performed on both the bond wafer to be the active layer of the SOI wafer to be the product and the monitor wafer. As for the bond wafer, a screen oxide film is then removed (e), and the base wafer and the bond wafer are cleaned and subsequently subjected to bonding heat treatment (g), for example, under an oxygen atmosphere through a bonding process (f). Thereafter, thinning the bond wafer is then performed by, for example, grinding and polishing (h), and are further polished and cleaned (i) to fabricate the product SOI wafer (l). As for the monitor wafer, it is subjected to heat treatment under a nitrogen atmosphere (g) separately from the SOI wafer to be the product and subsequently a screen oxide film is removed (j). The evaluation of the buried diffusion layer of the SOI wafer to be the product has been performed indirectly by measuring sheet resistance of a high-impurity concentration diffusion layer thus formed on the monitor wafer (k).
According to such a method, however, there has been a problem that the impurity concentration is likely to change depending on the atmosphere during the heat treatment.
Consequently, there has been proposed a method in which the monitor wafer having the same SOI structure as that of the product SOI wafer is fabricated, and after exposing the buried diffusion layer formed in this monitor wafer to a surface by grinding, polishing, etching, or the like, the buried diffusion layer of the product SOI wafer is evaluated by measuring the sheet resistance of the exposed buried diffusion layer.
According to the above-mentioned method, however, there has been problems that a cost for fabricating the monitor wafer is further increased, such that, a material cost or the number of processes is increased, due to fabricating the monitor wafer having the SOI structure other than the product SOI wafer.
Consequently, there has been disclosed a method in which the SOI structure of the monitor wafer is not completely reproduced, and after forming the impurity diffusion layer in the monitor wafer, processing is performed while a surface of this impurity diffusion layer is capped with a CVD film to then monitor the buried diffusion layer of the SOI wafer (Japanese Unexamined Patent Publication (Kokai) No. H7-111321).
However, it is still required to fabricate the monitor wafer even by the above-mentioned method, so that the problem of the cost, such as the material cost, the number of processes, or the like for fabricating the monitor wafer has not been solved yet.
Moreover, according to the above-described method for fabricating the monitor wafer to indirectly evaluate the sheet resistance of the buried diffusion layer of the product SOI wafer, since the product SOI wafer is not directly evaluated, quality assurance of the product SOI wafer has not been enough.